1. Field of the Invention
This invention relates to clock recovery circuits and more particularly to phase locked loops used to recover a clock and data from an input data stream.
2. Description of the Related Art
It is common to transmit data streams with an implied clock. When the data stream is decoded, the clock is extracted from the data and regenerated. The data is then resynchronized to the extracted clock. Traditionally, a phase locked loop (PLL) has been used to perform the clock recovery operation. FIG. 1A shows a block diagram of a traditional PLL configured for a clock and data recovery application. The phase locked loop 100 includes a phase detector 102, which receives the input data signal conveyed on node 104 and also receives the output clock signal conveyed on node 106 from the voltage controlled oscillator (VCO) 108. The phase detector 102 generates an error signal 110, which is a function of the phase difference between the input data signal and the VCO output clock signal. The phase detector 102 may also include additional circuitry to generate the reconstructed data on output node 114.
The loop amplifier and filter block 112 typically includes a gain block 120, an integrator block 122, and a summer block 124, shown in FIG. 1B. The loop amplifier and filter block 112 low-pass filters the output of the phase detector 102 to generate a control signal on node 116 that is provided to the VCO 108. VCO 108 adjusts the output clock signal on node 106 in response to the control signal to track the input data signal.
In data/clock recovery systems, traditional PLLs have two significant drawbacks. First, the stabilizing zero in the loop gain equation produces jitter peaking in the closed loop transfer response. In order to appreciate this issue, a brief description of the frequency response of the traditional PLL is set forth. FIG. 1C, illustrates the linear block diagram of the PLL shown in FIG. 1A. Equation 1 sets forth the closed loop transfer function, G(s), of traditional PLL 100, where τ1 is the time constant of the explicit zero and K1 is the combined gain of the loop amplifier and filter, the phase detector and the VCO.
                              G          ⁡                      (            s            )                          =                                            K              1                        ⁡                          (                              1                +                                                      τ                    1                                    ⁢                  s                                            )                                                          s              2                        +                                          K                1                            ⁢                              τ                1                            ⁢              s                        +                          K              1                                                          (                  Eq          .                                          ⁢          1                )            
FIG. 2 shows a graph of the frequency response of the closed loop transfer function. As can be seen in the graph, the magnitude of the transfer function is fairly constant at low frequency, and increases slightly for a band of frequencies labeled 200, where the transfer function exceeds unity and results in jitter peaking.
The magnitude of that peaking is very critical for many applications. For example, the Synchronous Optical Network (SONET) standard limits the acceptable peaking to 0.1 dB. If allowed to exceed this limit, frequency components of input data jitter which fall within this peaking region are actually amplified by the PLL. If several such PLLs are coupled sequentially, the jitter may be amplified to a degree which severely compromises the ability to meet jitter tolerances, or even to correctly recover data.
A second problem characteristic of traditional PLLs is that the jitter tolerance and the jitter transfer characteristic are both tied to the same circuit parameter (gain K1) and cannot be independently optimized.
A solution to the two problems described above was proposed in U.S. Pat. No. 5,036,298 to Bulzachelli. Unlike the traditional PLL system shown in FIG. 1, the system shown in FIG. 3 delays the incoming data on node 303 by an amount determined by the control voltage on node 305. Note that the incoming data is regenerated by additional logic in phase detector 309 and is retimed to be synchronous with the output clock from VCO 311 on node 312. It is desirable for the system shown in FIG. 3 that the delay provided be a well controlled delay with respect to voltage, independent of the input data pattern. That can be difficult for high speed applications whose circuits do not completely reach a static condition between input transitions.
Therefore, it would be desirable to solve the jitter peaking problem for high speed applications while avoiding the data pattern dependencies associated with prior art PLL structures.